By Bernhard Goll
This e-book covers the whole spectrum of the basics of clocked, regenerative comparators, their cutting-edge, complicated CMOS applied sciences, cutting edge comparators inclusive circuit elements, their characterization and houses. ranging from the fundamentals of comparators and the transistor features in nanometer CMOS, seven high-performance comparators built via the authors in 120nm and 65nm CMOS are defined widely. tools and dimension circuits for the characterization of complicated comparators are brought. A synthesis of the principally differing features of calls for on sleek comparators and the houses of units being to be had in nanometer CMOS, that are posed via the so-called nanometer hell of physics, is finished. The e-book summarizes the state-of-the-art in built-in comparators. complex dimension circuits for characterization should be brought in addition to the tactic of characterization through bit-error research often getting used for characterization of optical receivers. The e-book is compact, and the graphical caliber of the illustrations is exceptional. This publication is written for engineers and researchers in in addition to scientists and Ph.D scholars at universities. it's also recommendable to graduate scholars specializing on nanoelectronics and microelectronics or circuit layout.
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Extra info for Comparators in Nanometer CMOS Technology
18. The comparator metastability in the presence of noise is mathematically treated in . 5 for a low) occurs. Therefore the mean voltage value of this bit stream is located in the middle between the voltage level for the logical high and low. 5, which means that half of the decisions are correct. Between two comparison phases the comparator has to be reseted. So there exists additional logic in the inverter chains, which holds the decision during reset. For BER measurements it is often easier to use one output of the comparator only as shown in Fig.
Typically the following logic gate of the chain of inverters has another switching threshold than the operating point of the latch in the comparator. So it happens that COUT and COUT have the same logic voltage value when a metastability error occurs, but a valid logic level. 4 Characterization of Comparators 35 BER Analyzer CLK COUT PRBS generator Vref ± Noise N(t) OUT 0 Inverter chain (logic gates) Vref OUT COUT Comparator Synchronous data V0 VSS VDD CLK VSS VDD OUT OUT Comparison Reset Vref t Valid decisions due to a large V0 VSS Metastability error t Switching threshold VST of inverter chain Operating point VOP of latch t Valid decision due to noise Fig.
Taking care of different delay times of cables then with an oscilloscope the offset and hysteresis of the comparator can be determined, as depicted in principle for different cases in Fig. 11. In  the sensitivity and the maximum clock frequency of a clocked, regenerative comparator was measured by a so-called overdrive recovery test. At the negative input a precise, variable reference voltage was applied. At the positive input a synchronous square wave signal with a frequency of 1/8 of the clock frequency was applied.