Arithmetic Built-In Self-Test for Embedded Systems by Janusz Rajski

By Janusz Rajski

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A hardware used to implement the bit-flipping or bit-fixing sequence generation logic is a major cost of this approach, as it has to be customized for a given CUT and LFSR. On the other hand, there are trade-offs between the hardware overhead and the LFSR size as well as the test length. Consequently, the LFSR can be chosen such that the area required for implementation is minimized, and increase in a number of pseudo-random patterns may also result in a smaller BIST circuitry. 30 1. 13: Scan chain used to encode test patterns.

Again, a straightforward way to obtain this statistic is to simulate the CUT using the actual test patterns. If simulation is not possible, signatures from a number of circuits can be collected and the mosi common one picked. In next two subsections, we describe the most pop­ ular compaction schemes and techniques employed to evaluate their properties, in particular the aliasing probability they introduce. A thorough analysis of compaction schemes and related theoretical results can be found in [131].

3 Error Models and Aliasing How likely is it that a fault will generate a signature identical to a fault-free signature? To answer this fundamental question, numerous approaches have been proposed to derive a closed-form solution for the aliasing probability. Since detailed circuit simulation may not be practical, the aliasing probability is often estimated based on probabilistic models of erroneous sequence generated by faulty circuits. These error models reflect some basic features of the CUT and can be generally divided into two groups: those describing single streams of bits for single-input compaction schemes, and models used for multiple-input compactors.

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